In general, PCBA processing requires the selection of a dust-free and anti-static workshop. Temperature and humidity have control objectives, and there is no requirement for cutting feet.
For SMT processing, the control of the soldering temperature is very important. Generally, the manual soldering temperature should be kept within the range of 240-280 degrees. The difference between the set temperature and the temperature of the soldering iron should be as small as possible.
If the equipment welding preheating zone, heat preservation zone, reflow zone and cooling zone are different, it is very difficult to grasp according to different boards. This process is still complicated, and it is necessary to have strong and experienced SMT manufacturers to ensure The process is stable.
The reason why the circuit board PCBA processed the wave soldering time-space welding is as follows:
1. The PCB design is unreasonable with a shadow effect;
2, PCB deformation;
3. The PCB is oxidized and damp;
4. The height of the peak is not parallel to the circuit board;
5, the peak height is too high (if it is the electromagnetic pump peak machine).
This is generally a problem with one or more of the above problems.
PCB fabrication is classified according to the function of the holes. From the perspective of function, the vias can be divided into two types: one is used as an electrical connection between the layers; the other is used for fixing or positioning the device.
In terms of PCB manufacturing process, these vias are generally divided into three types, namely, blind vias, buried vias, and through vias.
The blind holes are located on the top and bottom surfaces of the printed wiring board and have a depth for the connection of the surface lines and the underlying inner lines, and the depth of the holes usually does not exceed a certain ratio (aperture).
Buried hole refers to a connection hole located in the inner layer of the printed wiring board, which does not extend to the surface of the circuit board. The above two types of holes are located in the inner layer of the circuit board, and are completed by a through hole forming process before lamination, and several inner layers may be overlapped during the formation of the via holes.
The third type is called a through hole, and the hole passes through the entire circuit board and can be used to implement internal interconnection or as a mounting hole for the component. Since the vias are easier to implement in the process and lower in cost, most printed circuit boards use it without the need for two other vias.
High-speed PCB design needs to pay attention to the following issues:
First, the impact of wiring topology on signal integrity
Signal integrity issues can occur when signals are transmitted along a transmission line on a high speed PCB. STMicroelectronics user tongyang asked: For a group of buses (address, data, command) to drive up to 4 or 5 devices (FLASH, SDRAM, etc.), in the PCB wiring, the bus arrives at each device in turn, such as Connected to SDRAM, then to FLASH... or the bus is star-shaped, that is, separated from somewhere and connected to each device. These two methods are in signal integrity.
In this regard, Li Baolong pointed out that the influence of the wiring topology on signal integrity is mainly reflected in the inconsistency of the signal arrival times at each node, and the timing at which the reflected signals arrive at a certain node is also inconsistent, resulting in deterioration of signal quality. In general, the star topology can control the signal transmission and reflection delay by controlling several branches of the same length to achieve better signal quality. Between the use of the topology, the signal topology node conditions, the actual working principle and the wiring difficulty should be considered. Different Buffers have different effects on the reflection of signals. Therefore, the star topology does not solve the delay of connecting the above data address bus to FLASH and SDRAM, so that the quality of the signal cannot be ensured. On the other hand, the high-speed signal is generally Communication between DSP and SDRAM, FLASH loading rate is not high, so in the high-speed simulation, as long as the waveform of the node where the actual high-speed signal works effectively, without paying attention to the waveform at the FLASH; star topology comparison daisy chain and other topologies It is difficult to route, especially when a large number of data address signals are in a star topology.
Second, the impact of the pad on high-speed signals
In the PCB, from the design point of view, a via is mainly composed of two parts: the middle hole and the pad around the hole. An engineer named fulonm asked the guest pad how it affects high-speed signals. In this regard, Li Baolong said: The pad has an impact on high-speed signals, which affects the impact of device-like packages on the device. Detailed analysis, after the signal comes out of the IC, through the bonding wires, pins, package casing, pads, solder to the transmission line, all the joints in this process will affect the signal quality. However, in actual analysis, it is difficult to give specific parameters for pads, solders, and pins. Therefore, they are generally summarized by the parameters of the package in the IBIS model. Of course, such analysis can be received at lower frequencies, but higher precision simulations for higher frequency signals are not accurate enough. A current trend is to describe the Buffer characteristics using the V-I and V-T curves of IBIS and the package parameters using the SPICE model.
Third, how to suppress electromagnetic interference
PCB is the source of electromagnetic interference (EMI), so PCB design is directly related to the electromagnetic compatibility (EMC) of electronic products. Focusing on EMC/EMI in high-speed PCB design will help shorten product development cycles and speed time-to-market. Therefore, many engineers are very concerned about the problem of suppressing electromagnetic interference in this forum. For example, Shu Jian of Wuxi Xiangsheng Medical Imaging Co., Ltd. said that in the EMC test, the harmonics of the clock signal were found to be very serious. Is it necessary to special treatment of the power supply pin of the IC using the clock signal? A decoupling capacitor is connected to the power supply pin. In the PCB design, what aspects should be paid attention to to suppress electromagnetic radiation? In this regard, Li Baolong pointed out that the three elements of EMC are radiation sources, transmission routes and victims. The propagation route is divided into space radiation propagation and cable conduction. So to suppress the harmonics, first look at the way it spreads. Power supply decoupling is to address conduction propagation and, in addition, the necessary matching and shielding is also required.
Li Baolong also pointed out that the question of WHITE users pointed out that filtering is a good way to solve the problem of EMC radiation through conduction. In addition, it can also be considered from the source of interference and the victim. For interference sources, try to use an oscilloscope to check if the rising edge of the signal is too fast. There is reflection or Overshoot, undershoot or ringing. If there is, you can consider matching. Also try to avoid the 50% duty cycle signal, because this signal is not even. Subharmonic, more high frequency components. In terms of victims, measures such as land acquisition can be considered.
Fourth, RF wiring is to choose through holes or bend wiring
In this regard, Li Baolong pointed out that the analysis of the return path of the RF circuit is not the same as the signal return in the high-speed digital circuit. What they have in common is the distributed parameter circuit, which is the characteristic of the calculation circuit using Maxwell equation. However, the RF circuit is an analog circuit. There are two variables in the circuit: voltage V=V(t) and current I=I(t). The digital circuit only needs to pay attention to the change of the signal voltage V=V(t). Therefore, in the RF wiring, in addition to considering the signal reflow, it is also necessary to consider the influence of the wiring on the current. That is, the bend wiring and vias have no effect on the signal current. In addition, most RF boards are single-sided or double-sided PCBs, and there is no complete planar layer. The return path is distributed around the signal and the power supply. When simulating, it needs to be analyzed by 3D field extraction tool. The reflow of vias requires specific analysis; high-speed digital circuit analysis typically only processes multi-layer PCBs with complete planar layers, using 2D field extraction analysis, only considering signal reflow in adjacent planes, vias only as a lumped parameter RLC deal with.
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