Because the PCB production engineer and the PCB design engineer have different understandings of the PCB, the GERBER file converted by the PCB factory may not be what you want.
If you design the component parameters in the PCB file, you don't want these. The parameters are displayed on the finished PCB. You have not explained it.
The PCB factory has left these parameters on the finished PCB according to the gourd painting. This is just an example.
This can be avoided if you convert the PCB file to a GERBER file yourself. The GERBER file is an international standard lithography format file, which includes RS-274-D and RS-274-X formats.
RS-274-D is called the basic GERBER format and must be accompanied by a D code file. A complete description of a graphic; RS-274-X is called the extended GERBER format, which itself contains D code information.
Commonly used CAD software can generate these two format files. How to check the correctness of the generated GERBER? You only need to import these GERBER files and D code files in the free software Viewmate V6.3 to see them on the screen or through the printer.
The drilling data can also be generated by various CAD software, the general format is Excellon, in Viewmate It can also be displayed. Without drilling data, of course, you can't make PCBs.
Compared with the characteristics of HDI technology, the biggest advantage of ALIVH is that the degree of freedom of design is greatly increased, and it can be arbitrarily punched between layers, and the HDI process cannot do this.
Generally, the most complicated structure of domestic manufacturers is that the design limit of HDI is a third-order HDI board. Since HDI is not completely laser-drilled, the buried hole in the inner layer is a mechanical hole, so the requirement of the hole plate is better than that of the laser hole.
It is much larger, and the mechanical hole takes up space on the level through which it passes. Therefore, in general, the structure of HDI is more punctured than the ALIVH technology, and the aperture of the inner core plate can also be widely used with 0.2 mm micropores.
Therefore, the wiring space of the ALIVH board is much higher than that of the HDI. At the same time, the cost and processing difficulty of ALIVH is also higher than that of HDI.
Any layer via technology completely overturns the traditional via design approach. If you still need to set up different layers of vias, it will increase the management difficulty. Design tools are required to have intelligent punching capabilities, while being able to combine and split at will.
Cadence adds a layering method based on the Working Layer in the traditional wiring layer-based wiring method. You can select the layer that can be looped in the Working Layer panel, and then select any layer when you double-click the hole. Change the line between.High-speed access to the Internet and social networks requires high integration and miniaturization of handheld devices.
Currently relying on the most advanced 4-N-4 HDI technology. But for the next generation of new technologies, achieving higher interconnect densities, in this area, the inclusion of passive or even active parts into the PCB and substrate can meet the above requirements.
When you design consumer electronics such as mobile phones and digital cameras, it is the best choice for current designs to consider how to embed passive and active parts into PCBs and substrates.
This approach may be slightly different because you are using a different vendor. Another benefit of embedding parts is that the technology provides protection against intellectual property and prevents so-called reverse design.
Allegro PCB Editor offers the best industrial grade solutions. Allegro PCB Editor also works more closely with HDI boards, flex boards and embedded parts. You can get the correct parameters and constraints to complete the design of the embedded part.
The design of the embedded device not only simplifies the process of the latter SMT, but also greatl
improves the cleanliness of the product.With the development of high-speed serial bus technology, the signal transmission rate continues to increase, and the influence of via parasitic parameters is also receiving more and more attention.
High-speed simulation engineers focus on via optimization and reduce the effects of via parasitic parameters by various means. Due to the design requirements of the hole in the disk, HDI can reduce the parasitic parameters of the surface device.
At the same time, the inductance and capacitance of the microvia are only about one tenth of a standard via. There are still many problems. The parasitic capacitance is the capacitance to the ground. The mechanical hole does not connect the ground plane to the 6 layers.
The calculation will be far more than the calculation. The formula is complicated; in the current production of vias, the diskless process is basically used, that is, the via pads of the non-connected layer are removed, which can effectively reduce the parasitic capacitance of the vias.
In this case, it is not enough to simply consider the influence of the characteristic impedance of the via.